1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a dynamic threshold (DT) complimentary metal oxide semiconductor (CMOS) field effect transistor (FET) device and method for forming same.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced. High device density also requires low-power operation.
The push for ever increasing device densities is particularly strong in CMOS technologies, such as in the design and fabrication of field effect transistors. FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.). Unfortunately, increased device density in CMOS FETs can result in degradation of performance and/or reliability.
One type of FET that has been proposed to facilitate increased device density is a dynamic threshold CMOS field effect transistor. Dynamic thresholding is achieved by electrically connecting the gate to the body, so that the body voltage moves with the gate voltage, lowering the threshold voltage when a signal is present. Dynamic thresholding provides faster response time and lower power consumption for the FET. Threshold voltage (Vt) is high in the off-state, limiting power leakage, and low in the on-state, limiting power requirements. CMOS generally uses less power than ordinary MOS. Dynamic threshold CMOS uses less power than standard CMOS.
Unfortunately, several difficulties arise in the design and fabrication of DT CMOS FETs. First, the connection between the gate and the body contact in prior art DT CMOS FETs is inevitably a long, high-resistence path. That high resistence degrades the response time of the circuit. Second, the body-source/drain capacitance in existing DT CMOS FETs limits the speed of the circuit. Neither result is desirable in CMOS applications. Unfortunately, these two practical limitations counterbalance the response time increase otherwise available from dynamic threshold CMOS.
Thus, there is a need for improved device structures and methods of fabrications of DT CMOS devices that provide dynamic threshold operation without paying the performance cost of high resistence gate-body contact and high body-source/drain capacitance. Only then can the full potential of DT CMOS be realized.